The present invention relates generally to electrical digital pulse handling and, more specifically, to circuits which detect either a rising or falling signal edge on an input signal and generate output pulses in response to such input pulse transitions.
Clock producing or clock generating circuits wherein the circuit produces an output pulse in response to input pulse edge transitions are known in the prior art. Circuit elements which delay and/or invert electrical signals upon propagation therethrough have been used in one or both of parallel paths between input and output logic means in these clock generators. Such a conventional edge detector circuit 100 is shown in FIG. 1. Input signal receiving means 110 has first and second signal transmitting paths 120 and 130, respectively, connected thereto. First signal path 120 transmits signals substantially without delay. Second signal path 130 transmits signals with a predetermined delay caused by negative logic elements 131-135. These logic elements are commonly signal inverters. For each rising or falling input signal transition edge, circuit 100 will generate an output pulse through gating means 115, which is illustrated as a NAND gate having inputs from signal paths 120 and 130, and transmitted along signal path 140. The width of this output pulse is determined by the number and nature of inverters 131-135 in delay line 130, each of said inverter having a characteristic delay time. For convenience of discussion below, each of these inverters and NAND gate 115 will be assumed to create the same signal delay.
FIGS. 2A-2G illustrate ideal or theoretical square wave forms occurring in the circuit of FIG. 1 at the corresponding alphanumeric nodal locations in response to a step input signal. As the signal input through signal receiving means 110 changes from a low, or "0", to a high, or "1", voltage level, signal transition edge 110 is transmitted through undelayed signal path 120 to NAND gate 115 and through delayed signal path 130 to inverter 131. Passing through inverter 131, this input signal is inverted and time delayed, thus creating transition edge 220 which is input to inverter 132. Likewise, inverter 132 transmits an inverted and delayed signal having transition edge 230 to inverter 133, and so on through inverters 134 and 135 with transition edges 240 and 250, respectively.
When the input signal to circuit 100 has been low or high for a time longer than the total characteristic delay times of inverters 131-135, gate 115 is at one of its two "rest" states and the signal from delay path 130 to NAND gate 115 will be high or low, respectively. Initially, when transition edge 210 is input to NAND gate 115, a low output is produced with transition edge 280, as both NAND inputs are high. After the total delay period of path 130, transition edge 260 is input to NAND gate 115 and a high output is again produced with transition edge 270. The width of the output pulse defined between transition edges 270 and 280 is a function of the total delay time of path 130 and may be altered by selecting the appropriate number and type of inverters therein. For a given delay path, this and other standard "glitch makers" will generate an output pulse of substantially constant width, as long as the input signal does not have other edge transitions within the "delay" time, or the time it takes transition edge 210 to propagate through signal path 130.
The conventional edge detector may also be generally understood as follows. NAND gate 115 has, as mentioned above, two rest states during which a high signal is output. The waveforms illustrated in FIGS. 2A-2G represent the several intermediate states of the circuit in response to input signal transitions prior to reaching a rest state. If an input transition from 0 to 1 occurs at time T=0 then: at time T less than 0, path 120 input to gate 115 is 0, path 130 input to gate 115 is 1, and gate 115 output is 1; at T greater than 0 but less than the delay time, path 120 input to gate 115 is 1, path 130 input to gate 115 is still 1, and gate 115 output becomes 0; at T greater than the delay time, path 120 input to gate 115 remains 1, but path 130 input to gate 115 becomes 0, and, thus, gate 115 output returns to 1.
Note that the conventional edge detection shown in FIG. 1 and mentioned thus far is only a rising edge detector. For input signal transitions from 1 to 0, i.e., a falling edge, no output pulse would be produced by gate 115. For T between 0 and the delay time, paths 120 and 130 both input 0 to gate 115. At all other times, one path inputs a 1 while the other path inputs a 0. Thus, gate 115 always outputs a 1.
To create a conventional falling edge detector, inverter 350 may be included in circuit 300 at the input of conventional converter circuit 100, as shown in FIG. 3. To detect both rising and falling edge signal transitions, circuits 100 and 300 may be combined in parallel as shown in FIG. 4, sharing input signal receiving means 410 and terminating NAND gate 460.
Conventional edge detector circuits commonly have a problem if more than one input signal transition occurs in a time period less than the total delay line signal propagation time. FIGS. 5A-5G illustrate the ideal waveforms occurring in circuit 100 at the corresponding alphanumeric nodal locations in response to a rapidly changing step input signal. Input signal transitions are shown, for example, to occur at time intervals equivalent to twice the characteristic delay time of inverters 131-135. First input signal transition 510 starts a signal propagating in delay path 130, and next input signal transition 512 occurs before the signal from the first transition has finished progating down path 130. Thus, circuit 100 is not in its rest state when transition 512 occurs, and the full output pulse is not produced by NAND gate 115 in response to the last input signal transition.
More specifically, rising signal transition 510, falling signal transition 512, and rising signal transition 514 are input signals to circuit 100 and propagate down paths 120 and 130. Inverter 131 delays and inverts these signals so as to create falling transitions 520 and 524 and rising transition 522, corresponding to transitions 510, 514, and 512, respectively. Similarly, inverter 132 delays and inverts these signals from inverter 131 so as to create rising transitions 530 and 534 and falling edge 532 corresponding to rising transitions 510 and 514 and falling transition 512. Likewise, inverter 133 creates falling transitions 540 and 544 and rising transition 542, inverter 134 creates rising transitions 550 and 554 and falling transition 552, and inverter 135 creates falling transitions 560 and 564 and rising transition 562, each set of signals corresponding respectively to transitions 510, 514, and 512.
Path 130 inputs a high signal to NAND gate 115 while path 120 inputs signal transitions 510 to high, 512 to low, and 514 to high, thus causing gate 115 to output transitions 570, 572, and 574, respectively. Path 120 inputs a high signal to NAND gate 115 while path 130 inputs signal transitions 560 to low, 562 to high, and 564 to low, thus causing gate 115 to output transitions 576, 578, and 580, respectively. Since signal transitions in paths 120 and 130 are each separated by a period of time equal to twice the "unit delay", or the characteristic delay of each inverter, and the total delay time of path 130 results in the leading signal transition propagating down path 130 to be delayed a period of time equal to five times the unit delay, output signal transitions 574 and 576 create a narrow pulse 592 having only a single unit delay width.
When compared to the output signal of a single input signal transition, as shown in FIG. 2G, the rapid transition input signal produces a ripple effect of several short output signal pulses 591, 592, and 593. When input signal transitions are not ideal, but rather, have a discrete rising or falling time, this deficiency in conventional edge detectors is exacerbated. The delay path circuit elements and the terminating logic gate may not detect one input transition quickly enough before another input transition arrives, and, thus, fail to respond with any output pulse at all.
Such rapid transitions are not an uncommon occurrence and may be caused, for example, by noise on the address bus of a memory circuit chip prior to a stable address and may prevent the start of a full clocking cycle. This may present a serious problem since a memory chip must produce the correct output at a predetermined time after a valid address is presented. Conventional edge detector circuits have thus had to require the address inputs to be stable for some period of time before the true address is presented in order to allow the delay line circuitry to come to its rest state. Since the trend in electronic memory devices is to require faster and faster system response time and memory devices are commonly used in "noisy"environments, it is desirable to decrease this time as much as possible.